This invention relates to a semiconductor test system for testing semiconductor devices, and more particularly, to a semiconductor test system having a glitch detection means for detecting glitches in an output signal of a semiconductor device under test to accurately evaluate the performance of the device under test.
In testing semiconductor devices such as ICs and LSIs by a semiconductor test system, such as an IC tester, a semiconductor IC device to be tested is provided with test signals or test patterns produced by an IC tester at its appropriate pins at predetermined test timings. The IC tester receives output signals from the IC device under test in response to the test signals. The output signals are strobed or sampled by strobe signals with predetermined timings to be compared with expected data to determine whether the IC device functions correctly.
Traditionally, timings of the test signals and strobe signals are defined relative to a tester rate or a tester cycle of the semiconductor test system. Such a test system is sometimes called a cycle based test system. Another type of test system is called an event based test system wherein the desired test signals and strobe signals are produced by event data from an event memory directly on a per pin basis. The present invention is applicable to both cycle based test system and the event based test system.
An example of configuration of a traditional cycle based test system is shown in a block diagram of FIG. 1A. In this example, a test processor 11 is a dedicated processor provided within the semiconductor test system for controlling the operation of the test system through a tester bus. Based on pattern data from the test processor 11, a pattern generator 12 provides timing data and waveform data to a timing generator 13 and a wave formatter 14, respectively. A test pattern is produced by the wave formatter 14 with use of the waveform data from the pattern generator 12 and the timing data from the timing generator 13. The test pattern is supplied to a device under test (DUT) 19 through a driver 15 in a pin electronics 20.
A response signal from the DUT 19 resulted from the test pattern is converted to a logic signal by an analog comparator 16 in the pin electronics 20 with reference to a predetermined threshold voltage level. The logic signal is compared with expected value data from the pattern generator 12 by a logic comparator 17. The result of the logic comparison is stored in a failure memory 18 corresponding to the address of the DUT 19. As noted above, the driver 15, the analog comparator 16 as well as switches (not shown) for changing pins of the device under test, are provided in the pin electronics 20.
An example of configuration of an event based test system is shown in a block diagram of FIG. 1B. In an event based test system, notion of events is employed where events are any changes of the logic state in signals to be used for testing a semiconductor device under test. For example, such changes are rising and falling edges of test signals or timing edges of strobe signals. The timings of the events are defined with respect to a time difference from a reference time point. Typically, such a reference time point is a timing of the previous event. Alternatively, such a reference time point is a fixed start time common to all of the events.
In an event based test system, since the timing data in a timing memory (event memory) does not need to include complicated information regarding waveform, vector, delay and etc. at each and every test cycle, the description of the timing data can be dramatically simplified. In the event based test system, as noted above, typically, the timing (event) data for each event stored in an event memory is expressed by a time difference between the current event and the last event. Since such a time difference between the adjacent events (delta time) is small, unlike a time difference from a fixed start point (absolute time), a size of the data in the memory can also be small, resulting in the reduction of the memory capacity.
In the example of FIG. 1B, the event based test system includes a host computer 42 and a bus interface 43 both are connected to a system bus 44, an internal bus 45, an address control logic 48, a failure memory 47, an event memory consists of an event count memory 50 and an event vernier memory 51, an event summing and scaling logic 52, an event generator 24, and a pin electronics 26. The event based test system evaluates a semiconductor device under test (DUT) 28 connected to the pin electronics 26.
An example of the host computer 42 is a work station having a UNIX, Window NT or Linux operating system therein. The host computer 42 functions as a user interface to enable a user to instruct the start and stop operation of the test, to load a test program and other test conditions, or to perform test result analysis in the host computer. The host computer 42 interfaces with a hardware test system through the system bus 44 and the bus interface 43. Although not shown, the host computer 42 is preferably connected to a communication network to send or receive test information from other test systems or computer networks.
The internal bus 45 is a bus in the hardware test system and is commonly connected to most of the functional blocks such as the address control logic 48, failure memory 47, event summing and scaling logic 52, and event generator 24. An example of address control logic 48 is a tester processor which is exclusive to the hardware test system and is not accessible by a user. The address control logic 48 provides instructions to other functional blocks in the test system based on the test program and conditions from the host computer 42. The failure memory 47 stores test results, such as failure information of the DUT 28, in the addresses defined by the address control logic 48. The information stored in the failure memory 47 is used in the failure analysis stage of the device under test.
The address control logic 48 provides address data to the event count memory 50 and the event vernier memory 51 as shown in FIG. 1B. In an actual test system, a plurality of sets of event count memory and event vernier memory will be provided, each set of which corresponds to a test pin of the test system. The event count and vernier memories store the timing data for each event of the test signals and strobe signals. The event count memory 50 stores the timing data which is an integer multiple of the reference clock (integral part), and the event vernier memory 51 stores timing data which is a fraction of the reference clock (fractional part). In the preferred embodiment of the present invention, the timing data for each event is expressed by a time difference (delay time or delta time) from the previous event.
The event summing and scaling logic 52 is to produce data showing overall timing of each event based on the delta timing data from the event count memory 50 and event vernier memory 51. Basically, such overall timing data is produced by summing the integer multiple data and the fractional data. During the process of summing the timing data, a carry over operation of the fractional data (offset to the integer data) is also conducted in the event summing and scaling logic 52. Further during the process of producing the overall timing, timing data may be modified by a scaling factor so that the overall timing be modified accordingly.
The event generator 24 is to actually generate the events based on the overall timing data from the event summing and scaling logic 52. The events (test signals and strobe signals) thus generated are provided to the DUT 28 through the pin electronics 26. Basically, the pin electronics 26 is formed of a large number of components, each of which includes a driver and a comparator as well as switches to establish input and output relationships with respect to the DUT 28.
FIG. 2 is a block diagram showing a more detailed structure in the pin electronics 26 having a driver 35 and an analog comparator 36. The circuit configuration and operation of the pin electronics 20 in the cycle based test system of FIG. 1A is the same as this one. The event generator 24 produces drive events which are provided to an input pin of the DUT 28 as a test signal (test pattern) through the driver 35. The event generator 24 further produces a sampling event which is provided to the analog comparator 36 as a strobe signal for sampling an output signal of the DUT 28. The output signal of the analog comparator 36 is compared with the expected data from the event generator 24 by a pattern comparator 38. If there is a mismatch between the two, a failure signal is sent to the failure memory 47 in FIG. 1B.
FIG. 3A shows an example of circuit diagram of a semiconductor device to be tested, and FIGS. 3B-3D show waveforms involved in the circuit diagram of FIG. 3A. When a signal of FIG. 3B is provided to an input I1 and a clock of FIG. 3C is provided to an input I2, the device of FIG. 3A produces an output signal of FIG. 3D. As noted above with reference to FIG. 2, the output signal of FIG. 3D is sampled at strobe points to see whether it matches the expected output signal.
This situation is shown in FIGS. 4A-4D. The input, clock and output signals of the device under test are shown in FIGS. 4A-4C, respectively. The output signal of FIG. 4C is sampled by strobe signals of FIG. 4D at the timings shown by arrows therein. If the output signal matches the expected (simulated) output signal at all strobe points, the device under test is considered satisfactory and pass the current test pattern. In an actual device test, strobe timings are usually set to points immediately after the transition of the simulated output signal as in the example of FIG. 4D.
FIGS. 5A-5C show the situation where a faulty device produces a different output signal when receiving the same test pattern in the foregoing examples. FIG. 5A shows a simulated (expected) output signal while FIG. 5B shows an actual output signal from the device under test. The output signal of FIG. 5B is faulty because it includes glitches at shaded portions in the waveform. However, by the strobe timings of FIG. 5C, the test produces a pass result since all test points are correct. The faulty is not discovered unless a manufacturer modify the test program to detect the glitches in the output signal or until it is applied to a customer application. This process is costly to both the device manufacturer and the customer.
Therefore, it is an object of the present invention to provide a semiconductor test system having a glitch detection means for detecting a glitch in an output signal of a semiconductor device under test to accurately evaluate the output signal of the semiconductor device under test.
It is another object of the present invention to provide a semiconductor test system having a glitch detection unit which includes an edge counter for counting the number of edges in the output signal from the semiconductor device under test to compare a correct number of edges, thereby detecting a glitch in the output signal.
It is a further object of the present invention to provide a semiconductor test system having a glitch detection means for detecting a glitch in the output signal from the semiconductor device under test by using a large number of strobes within a cycle of the output signal.
It is a further object of the present invention to provide a semiconductor test system having a glitch detection means for detecting a glitch in the output signal from the semiconductor device under test by using a continuous strobe signal which continuously changes a phase (timing) within a cycle of the output signal.
The present invention is a semiconductor test system having a glitch detection means for detecting glitches in the output signal from the device under test to accurately evaluate the function and signal quality of the device under test. The glitch detection means includes an edge counter which counts the number of edges of the output signal which is compared with the number of edges in the expected output signal. If the number of edges is greater than that of the expected output signal, then it is determined that the output signal from the device under test contains a glitch therein. In another aspect, the glitch detection means includes means for generating a large number of strobes within a cycle of the output signal of the device under test or generating a continuous strobe whose timing (phase) continuously changes within a cycle of the output signal.
In the present invention, the semiconductor test system for testing a semiconductor device includes an event memory for storing event data of events which are any changes in intended signals to be generated for testing a semiconductor device under test (DUT), an event generator for producing the intended signals which are test patterns, strobe signals and expected patterns based on the event data from the event memory, a pin electronics provided between the event generator and the DUT for transmitting the test pattern from the event generator to the DUT and receiving an output signal of the DUT and sampling the output signal by timings of the strobe signals from the event generator, a pattern comparator for comparing sampled output data from the pin electronics with the expected patterns and producing a failure signal when there is a mismatch therebetween, and a glitch detection unit for receiving the output signal from the DUT and detecting a glitch in the output signal by counting a number of edges in the output signal and comparing the count number with an expected number of edges.
In another aspect of the present invention, the glitch in the output signal of the device under test is detected by using a large number of strobe signals within a cycle of the output signal. In a further aspect, the glitch in the output signal of the device under test is detected by using a continuous strobe whose timing (phase) continuously changes within a cycle of the output signal.
According to the present invention, the semiconductor test system has the glitch detection unit for effectively detecting glitches in the output signal from the device under test to accurately evaluate the device under test. The glitch detection unit in the first embodiment allows the test system to detect unexpected output transitions in the device under test while adding only a small amount of extra hardware to the test system. The glitch detection unit also enhances failure detection accuracy without requiring extensive test pattern generation or increasing a device test time. In the second embodiment, glitches can be accurately detected by either the multiple-strobe signals or the continuous strobe signals of the present invention. The second embodiment of the present invention is effective in detecting glitches in the output signal of the device under test without adding any hardware to the test system.